1. Field of the Invention
The present invention relates to a probe card for use in a test of an IC (integrated circuit) device in the form of a wafer, a die, etc. More particularly, the present invention relates to a probe card which uses a wiring pattern on a membrane to provide electrical connection between test channels of a testing apparatus and signal terminals of an IC device under test (hereinafter, also referred to as a "DUT").
2. Description of the Related Art
Recent advancement in semiconductor microfabrication has allowed a higher-speed, multiple-pin, high-performance IC device to be formed within a small area. Recent trend toward smaller portable equipment has demanded a smaller-volume mounting package for IC devices, and some small packages are already in practical use, such as CSP (Chip Scale Package) which employs a flip chip mounting method. Moreover, in order to meet the demand for a device realizing a smaller size with more pins, an "area pad" device has recently been proposed in which bonding pads (hereinafter, also referred to simply as "pads") are provided not only in the periphery of the device but over the entire surface of the device.
A probe card used for testing such IC devices is required to be capable of providing a very accurate waveform to, and rapidly and accurately reading a waveform from, the IC device via the densely-arranged pads.
Conventional probe cards can be generally classified into a needle type probe card having a pad connecting section formed of tungsten needles, and a membrane type probe card having a pad connecting section configured using microstrip-line signal wiring and tungsten contact bumps. While the needle type probe card is the mainstream in the industry, the use of the membrane type probe card is growing in recent years as the demand for high-speed, multiple-pin IC devices grows.
Examples of the conventional probe card have been described in, for example, U.S. Pat. No. 4,906,920, and "A BiCMOS Active Substrate ProbeCard Technology for Digital Testing" on ISSCC 1996 Technical Digest, p. 308. The former describes a method for ensuring the electrical connection of contact bumps. The latter describes a method for providing a test chip in the vicinity of contact bumps in order to realize high-speed testing. The test chip serves as an interface between a DUT and a testing apparatus by buffering test data from the DUT and compensating for the function of the testing apparatus (e.g., an LSI test system).
With the conventional membrane type probe, however, it is difficult to ensure the electrical connection of the contact bumps. Thus, it is required to establish satisfactory electrical connection between the DUT and the pads even when heights of the contact bumps provided on the membrane vary.
Moreover, when using the conventional membrane type probe, it is difficult to realize a high-speed testing due to physical distance from the testing apparatus. In order to test a multiple-pin DUT at a high speed, a novel structure is needed for placing the test chip closer to the contact bumps so as to obtain the satisfactory electrical connection. Typically, however, a length of a printed board section is several tens of centimeters, and a length of the pad connection section is several centimeters, whereby an electrical length (transmission time) Td for a signal from a tester channel to the pad of the DUT is several nanoseconds. In order to reduce the transmission time Td, the distance between the tester channel to the DUT needs to be further reduced.
However, a conventional testing apparatus (LSI test system) capable of testing a multiple-pin DUT is costly, and large in size and must therefore be placed distant from the DUT.
Moreover, the number of tester channels which can be obtained by the state-of-the-art technology is about 1000, being less than the number of pins which can be provided on an area pad device. As a result, the design of a semiconductor IC device is limited by the number of pins on the test apparatus.